1. Field of the Invention
Embodiments of the invention relate to multilevel conversion circuits that deliver multilevel voltages.
2. Description of the Related Art
FIG. 10 shows an example of a five-level conversion circuit using flying capacitors disclosed in Japanese Unexamined Patent Application Publication No. 2012-182974. This conversion circuit delivers five levels of voltage from a DC power supply composed of series-connected two DC single power supplies DP and DN having three terminals: positive terminal P, a zero terminal M, and a negative terminal N. A series circuit of semiconductor switches S1 through S4, each composed of antiparallel-connected diode and an IGBT, is connected between the positive terminal P and the negative terminal N of the DC power supply. In parallel to a series circuit of the semiconductor switches S2 and S3 connected are a series circuit of the semiconductor switches S5 and S6 and a capacitor C1 called a flying capacitor. An AC switch composed of reverse blocking IGBTs S15 and S16 that exhibits withstand voltage in a reversed direction is connected between the connection point between the semiconductor switches S5 and S6 and the zero terminal M that is a middle potential point of the DC power supply. An AC terminal U is the connection point between the semiconductor switches S2 and S3.
When the voltage Edcp and Edcn of the respective DC single power supplies DP and DN are each 2E and the voltage Vc1 across the capacitor C1 is controlled at E, the circuit having the construction described above delivers five levels of voltage at the AC terminal U. For instance, when the semiconductor switches S1, S2, S6, and S16 are in the ON state, a voltage 2E is delivered from the AC terminal U; when the semiconductor switches S1, S3, S6, and S16 are in the ON state, or the semiconductor switches S2 and S6 and the AC switch Sac are in the ON state, a voltage E is delivered; when the semiconductor switches S3 and S6 and the AC switch Sac are in the ON state, or the semiconductor switches S2 and S5 and the AC switch Sac are in the ON state, a voltage zero is delivered; when the semiconductor switches S2, S4, S5, and S15 are in the ON state, or the semiconductor switches S3 and S5 and the AC switch Sac are in the ON state, a voltage −E is delivered; and when the semiconductor switches S3, S4, S5, and S15 are in the ON state, a voltage −2E is delivered at the AC terminal U.
In this operation, there are two modes for deliver a voltage E from the AC terminal U in the direction of current toward the load. One of them is through a path 1: the semiconductor switch S1→the capacitor C1→the semiconductor switch S3; the other is through a path 2: the AC switch Sac→the semiconductor switch S6→the capacitor C1→the semiconductor switch S2. The capacitor C1 is charged through the path 1 and discharged through the path 2. The average voltage of the capacitor C1 can be controlled at the value E by detecting the voltage of the capacitor C1 and appropriately selecting the paths in order for the average value of the voltage to be E. There are similarly two paths for the mode to deliver a voltage −E from the AC terminal U, and the average voltage of the capacitor C1 can be controlled at the value E.
FIG. 11 shows an example of conversion circuit that is an extended conversion circuit of seven levels from the conversion circuit of five levels shown in FIG. 10. The seven level conversion circuit of FIG. 11 has a circuit construction to deliver seven levels of voltage from a DC power supply composed of DC single power supplies DP and DN and having three terminals of a positive terminal P, a zero terminal M, and a negative terminal N. Between the positive terminal P and the negative terminal N connected is a series circuit of semiconductor switches S1 through S6 each consisting of a diode and an IGBT antiparallel-connected with each other. In parallel to the series circuit of semiconductor switches S2 through S5 connected are a capacitor C2 and a series circuit of the semiconductor switches S7 and S8. In parallel to the series circuit of semiconductor switches S3 and S4 connected is a capacitor C1. Between the connection point between the semiconductor switches S7 and S8 and the zero terminal M, i.e. the middle potential point of the DC power supply, connected is an AC switch Sac consisting of antiparallel-connected reverse-blocking IGBTs S15 and S16 each exhibiting a withstand voltage in the reverse direction. The connection point between the semiconductor switches S3 and S4 is the AC terminal U.
In this circuit construction, when the voltages Edcp and Edcn of the DC single power supplies DP and DN are each 3E, and the voltage Vc1 across the capacitor C1 is controlled at E and the voltage Vc2 across the capacitor C2 is controlled at 2E, seven levels of voltages are delivered from the AC terminal U. For example, when the semiconductor switches S1 through S3 are in the ON state, a voltage 3E is delivered from the AC terminal U; when the semiconductor switches S1, S2, and S4 are in the ON state, a voltage 2E is delivered; when the semiconductor switches S1, S5, and S4 are in the ON state, a voltage E is delivered; when the AC switch Sac and the semiconductor switches S7, S2, and S3, or the AC switch Sac and the semiconductor switches S8, S5, and S4 are in the ON state, a voltage zero is delivered; when the AC switch Sac and the semiconductor switches S7, S2, and S4 are in the ON state, a voltage −E is delivered; when the AC switch Sac and the semiconductor switches S7, S5, and S4 are in the ON state, a voltage −2E is delivered; and when the semiconductor switches S4 through S6 are in the ON state, a voltage −3E is delivered from the AC terminal U. In detail, there are a plurality of control modes other than the ones describe above. They are, however, extended operation of the circuits shown in FIG. 11 and thus detailed description thereon is omitted here.
In this operation, there are two modes for delivering a voltage E from the AC terminal U. One of them is through a path 1: the semiconductor switch S1→the capacitor C2→the semiconductor switch S5→the semiconductor switch S4; the other is through a path 2: the AC switch Sac→the semiconductor switch S8→the capacitor C2→the semiconductor switch S2→the capacitor C1→the semiconductor switch S4. The capacitor C2 is charged through the path 1 and discharged through the path 2. The average voltage of the capacitor C2 can be controlled at the value 2E by detecting the voltage of the capacitor C2 and appropriately selecting the paths in order for the average value of the voltage to be 2E. There are similarly two paths for the mode to deliver a voltage −E from the AC terminal U, and the average voltage of the capacitor C2 can be controlled at the value 2E by appropriately selecting the paths.
There are two modes for delivering a voltage 2E from the AC terminal U. One of them is through a path 1: the semiconductor switch S1→the semiconductor switch S2→the capacitor C1→the semiconductor switch S4; the other is through a path 2: the semiconductor switch S1→the capacitor C2→the semiconductor switch S5→the capacitor C1→the semiconductor switch S3. The capacitor C1 is charged through the path 1 and discharged through the path 2. The average voltage of the capacitor C1 can be controlled at the value E by detecting the voltage of the capacitor C1 and appropriately selecting the paths in order for the average value of the voltage to be E. There are similarly two paths for the mode to deliver a voltage −2E from the AC terminal U, and the average voltage of the capacitor C1 can be controlled at the value E.
In the seven-level conversion circuit having the construction of FIG. 11, the semiconductor switches S7 and S8 conduct switching with a voltage variation step of two units, i.e. 2E. A large voltage variation in an output waveform generally produces a high micro surge voltage on an AC motor, for example, in the load side corresponding to the voltage variation, causing a problem of dielectric breakdown.
In order to deal with this problem, the inventor of the present invention has proposed the circuit disclosed in Japanese Unexamined Patent Application Publication No. 2013-146117. FIG. 12 shows the construction of the circuit, in which a DC power supply consisting of series-connected DC single power supplies DP and DN has terminals of a positive terminal P, a zero terminal M, and a negative terminal N in the order of descending electric potential. The terminal M is the base terminal at a potential of zero. Semiconductor switches in the following description are IGBTs each having an antiparallel-connected diode. The other types of semiconductor switchers can be employed, of course. A series circuit of semiconductor switches S1 through S6 are connected between the positive terminal P and the negative terminal N. The connection point between the semiconductor switches S3 and S4 is an AC terminal U. A series circuit of semiconductor switches S7 through S10 and a capacitor C2 are connected between the connection point between the semiconductor switches S1 and S2 and the connection point between the semiconductors switches S5 and S6. An AC switch Sac composed of antiparallel-connected reverse blocking IGBTs S15 and S16 is connected between the zero terminal M and the connection point between the semiconductor switches S8 and S9.
Further, a capacitor C1 is connected between the higher potential terminal of the semiconductor switch S3 and the lower potential terminal of the semiconductor switch S4, and a capacitor C3 is connected between the higher potential terminal of the semiconductor switch S8 and the lower potential terminal of the semiconductor switch S9. The capacitors C1, C2, and C3 are called flying capacitors. The AC switch Sac can be composed, in place of using the construction of antiparallel connection of the semiconductor switches S15 and S16 each exhibiting reverse-blocking ability shown in FIG. 12, by combination of IGBTs without reverse-blocking ability and diodes as shown in FIGS. 13A-13C. The circuit in FIG. 13A is composed of antiparallel-connected two series circuits each consisting of a diode and an IGBT. The circuits in FIGS. 13B and 13C are composed of two circuits connected in series, each circuit consisting of antiparallel-connected diode and an IGBT.
The magnitude of the voltage of each of the DC single power supplies DP and DN in the circuit of FIG. 12 is supposed here to be 3E. Similarly to the conventional example of FIG. 11, the voltages Vc1, Vc2, and Vc3 of the capacitors C1, C2, and C3 are changed by charging or discharging the capacitors to hold average values of Vc1=E, Vc2=2E, and Vc3=E. When the potential at the zero terminal M is zero, the output voltage Vu at the AC terminal U can be obtained at seven levels of ±3E, ±2E, ±E, and zero by ON/OFF operation of the semiconductor switches. For example, when the semiconductor switches S1, S2, S3, S9, S10, and S16 are in an ON state and the other semiconductor switches are in an OFF state, as shown in FIG. 14A, the output voltage at the AC terminal U is +3E, which is the voltage at the terminal P of the DC single power supply DP. When the semiconductor switches S1, S3, S5, S9, S10, and S16 are in the ON state and the other semiconductor switches are in the OFF state as shown in FIG. 14B, the output voltage at the AC terminal U is +2E, which is the voltage +3E of the DC single power supply DP minus the voltage +2E of the capacitor voltage Vc2 plus the voltage +E of the capacitor voltage Vc1.
When the semiconductor switches S3, S5, S9, S10, S15, and S16 are in the ON state and the other semiconductor swathes are in the OFF state as shown in FIG. 14C, the output voltage at the AC terminal U is +E, which is the potential zero at the terminal M of the DC power supply plus the voltage +E of the capacitor voltage Vc1. When the semiconductor switches S4, S5, S9, S10, S15, and S16 are in the ON state and the other semiconductor switches are in the OFF state as shown in FIG. 14D the output voltage at the AC terminal U is zero, which is the potential at the terminal M of the DC power supply. When the semiconductor switches S3, S5, S7, S9, S15, and S16 are in the ON state and the other semiconductor switches are in the OFF state as shown in FIG. 14E, the output voltage at the AC terminal U is zero, which is the voltage zero at the terminal M of the DC power supply plus the voltage +1E of the capacitor voltage Vc3 minus the voltage +2E of the capacitor voltage Vc2 plus the voltage +1E of the capacitor voltage Vc1.
Electric current flows from the terminal P, M, or N to the AC terminal U as a result of ON/OFF operation of the semiconductor switches in the paths shown in FIGS. 14A through 14E, while charging or discharging the capacitors. There are a multiple of paths for a mode to obtain the same voltage at the AC output terminal similarly to the five-level conversion circuit of FIG. 10 and the seven-level conversion circuit of FIG. 11. By detecting the voltages of the capacitors and selecting an appropriate path, the voltage control is possible for the capacitors C1 and C3 in FIG. 12 at E and the capacitor C2 at 2E. Other combination of paths can deliver a desired voltage and charge or discharge the capacitors, through details are omitted here.
The conversion circuit of FIG. 12 provides seven levels of output voltages Vu from the DC power supply having three levels of potential terminals combining the voltages Edcp and Edcn of the DC single power supplies DP and DN and the voltages Vc1, Vc2, and Vc3 of the capacitors C1, C2, and C3 by means of ON/OFF operation of the semiconductor switches. In order to obtain seven levels of output voltages, the average value of the voltage Vc1 across the capacitor C1 is necessarily E, the average value of the voltage Vc2 across the capacitor C2 is necessarily 2E, and the average value of the voltage Vc3 across the capacitor C3 is necessarily E. In actual operation of the circuit, however, the capacitor voltages Vc1, Vc2, and Vc3 change due to the current running in the circuit. In generally employed method for holding the capacitor voltages at the average values, ON/OFF operation of the semiconductor switches S1 through S10 and the AC switch Sac is combined to deliver desired voltages and simultaneously control charging and discharging of the capacitors C1, C2, and C3. This control needs a means for detecting the capacitor voltages Vc1, Vc2, and Vc3. Nevertheless, the capacitors have no common potential part. Thus, the voltage detecting circuit needs an insulating function, which increases device costs.